The present invention relates to complementary metal-oxide semiconductor (CMOS) technology, and more specifically, to selective thickening of p-type or p-channel field effect transistor (pFET) dielectric.
A CMOS device typically includes complementary and symmetrical pairs of p-type and n-type metal oxide semiconductor field effect transistors (MOSFETs) or a pFET and n-type or n-channel FET (nFET) pair. Negative-bias temperature instability (NBTI) is a reliability issue in the pFET region or area of the CMOS device in particular and manifests as an increase in threshold voltage and corresponding decrease in drain current. NBTI limits the scaling of inversion layer thickness (Tinv).